On the design of fast, easily testable ALU's

On the Design of Fast , Easily Testable ALU

A design methodology for implementing fast, easily testable arithmetic-logic units (ALU’s) is presented. Here, we describe a set of fast adder designs, which are testable with a test set that has either ( ) complexity (Lin-testable) or (1) complexity (C-testable), where is the input operand size of the ALU. The various levels of testability are achieved by exploiting some inherent properties of...

Designing of Testable Reversible QCA Circuits Using a New Reversible MUX 2×1

Recently testing of Quantum-dot Cellular Automata (QCA) Circuits has attracted a lot of attention. In this paper, QCA is investigated for testable implementations of reversible logic. To amplify testability in Reversible QCA circuits, a test method regarding to Built In Self Test technique is developed for detecting all simulated defects. A new Reversible QCA MUX 2×1 desig...

Design of a fast, easily testable ALU

Designing of Testable Reversible QCA Circuits Using a New Reversible MUX 2×1

Recently testing of Quantum-dot Cellular Automata (QCA) Circuits has attracted a lot of attention. In this paper, QCA is investigated for testable implementations of reversible logic. To amplify testability in Reversible QCA circuits, a test method regarding to Built In Self Test technique is developed for detecting all simulated defects. A new Reversible QCA MUX 2×1 desig...

Easily Testable Array Multiplier Design Using Vhdl

Presents the design of variable array multipliers using VHDL. Multipliers of various operand sizes for different target processes can be implemented using the proposed VHDL based approach. The multipliers will be testable with a constant number of test vectors irrespective of the operand word lengths. A fast test pattern generator is also developed for simulation of the multiplier designs and s...